The present invention relates to semiconductor devices having multiple semiconductor chips layered on one another and manufacturing methods thereof. The invention more particularly relates to a semiconductor device including two semiconductor chips having their circuit forming surfaces opposed to one another, and electrodes formed on the circuit forming surfaces being electrically connected with one another, and a manufacturing method thereof.
In recent years, with the advent of smaller size electronic devices capable of high speed processing, a three-dimensional structure including two or more kinds of semiconductor chips layered on one another has come to be widely researched and developed.
Such a conventional three-dimensional semiconductor device will be now described.
FIG. 18 is a sectional view of the conventional semiconductor device.
As shown in FIG. 18, the conventional semiconductor device includes a first semiconductor chip 1 and a second semiconductor chip 4. The first semiconductor chip 1 has first electrodes 2 and bonding pads 3 on a first main surface. The second semiconductor chip 4 is provided with second electrodes 5 on a second main surface and has a smaller area than the first semiconductor chip 1. Herein, the first and second semiconductor chips 1 and 4 are integrated so that their main surfaces (i.e., the circuit forming surfaces) are opposed to one another and the first and second electrodes 2 and 5 are electrically connected with one another. Stated differently, while the first and second electrodes 2 and 5 are registered, the second semiconductor chip 4 is placed facedown on the first semiconductor chip 1. More specifically, the first and second electrodes 2 and 5 are connected through a metal bump 7, while the part of the second electrode 5 in contact with the metal bump 7 is provided with a barrier metal layer 6. The bonding pads 3 are provided outside the region of the first main surface of the first semiconductor chip 1 opposed to the second main surface of the second semiconductor chip 4. There is a resin layer 8 filled between the first main surface of the first semiconductor chip 1 and the second main surface of the second semiconductor chip 4. More specifically, the first and second semiconductor chips 1 and 4 are adhered by the resin layer 8 into an integrated form.
The surface of the first semiconductor chip 1 opposite to the first main surface is secured to a die pad portion 9a by conductive paste 10 containing palladium (Pd), silver (Ag) or the like. The bonding pad 3, and a lead portion 9b provided adjacent to the die pad portion 9a are electrically connected with one another through a thin metal bonding wire 11. Note that the die pad portion 9a and the lead portion 9b are cut from a single lead frame 9. The first and second semiconductor chips 1 and 4, the die pad portion 9a, the lead portions 9b and the bonding wires 11 are encapsulated in a resin package 12.
A method of manufacturing the conventional semiconductor device will be now described.
FIGS. 19A, 19B, 20A and 20B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
As shown in FIG. 19A, the first and second semiconductor chips 1 and 4 are registered. More specifically, a plurality of first electrodes 2 and a plurality of bonding pads 3 are provided on a first main surface of the first semiconductor chip 1. The chip 1 is then placed on a packaging jig (not shown) and a resin 8A is applied on the first main surface of the semiconductor chip 1. The second semiconductor chip 4 having a plurality of second electrodes 5 on a second main surface is prepared over the first semiconductor chip 1 so that their main surfaces, i.e., their circuit forming surfaces are opposed to one another. Then, after a plurality of metal bumps 7 are formed on the second electrodes 5, the first and second electrodes 2 and 5 are registered. Note that there is a barrier metal layer 6 provided on the part of the second electrodes 5 in contact with the metal bumps 7.
Then, as shown in FIG. 19B, the first and second semiconductor chips 1 and 4 are joined with one another. More specifically, the second semiconductor chip 4 is heated and pressed using a metal tool 13 from the surface opposite to the second main surface. As a result, the first electrodes 2 on the first semiconductor chip 1 and the second electrodes 5 on the second semiconductor chip 4 are joined with one another through the metal bumps 7 formed on the second electrodes 5 (more precisely on the barrier metal layers 6) on the second semiconductor chip 4. Then, the resin 8A filled between the joined first and second semiconductor chips 1 and 4 is irradiated with ultraviolet rays or heated for curing and a resin layer 8 results.
Then, as shown in FIG. 20A, the joined first and second semiconductor chips 1 and 4 in an integrated form (hereinafter referred to as a xe2x80x9cchip-layered bodyxe2x80x9d) is subjected to wire-bonding. More specifically, a lead frame 9 having a die pad portion 9a and lead portions 9b is prepared. Then, the surface opposite to the first main surface of the first semiconductor chip 1 is secured onto the die pad portion 9a using conductive paste 10 containing Pd, Ag or the like. The bonding pads 3 on the first semiconductor chip 1 and the lead portions 9b are then electrically connected through thin metal bonding wires 11. Thus, the electrical connection for the semiconductor device is completed.
As shown in FIG. 20B, the chip-layered body after the wire-bonding step is encapsulated in a resin. More specifically, the first and second semiconductor chips 1 and 4, the die pad portion 9a, the lead portions 9b and the bonding wires 11 are encapsulated in a resin package 12. Note however that the bottom surface of the die pad portion 9a and the bottom and outer side surfaces of the lead portions 9b (the side surfaces opposite to the side facing the die pad portion 9a) are exposed out of the resin package 12. Thus, the bottom and outer side surfaces of the lead portions 9b serve as external terminals.
However, the conventional semiconductor device and the manufacturing method thereof described above suffer from the following disadvantages. The thickness of the semiconductor device having multiple layers of semiconductor chips increases in proportion to the number of the semiconductor chips used. For example, in the conventional semiconductor device shown in FIG. 18, the thickness of the first and second semiconductor chips 1 and 4 is each about in the range from 200 to 300 xcexcm even after the back surface (the surface opposite to the circuit forming surface (main surface)) is polished. The metal bumps 7 used to join the first and second semiconductor chips 1 and 4 are about as thick as several tens xcexcm after the joining. In addition, if the chip-layered body including the first and second semiconductor chips 1 and 4 is die-bonded to the die pad portion 9a as thick as several hundreds xcexcm and the die-bonded chip-layered body as a whole is encapsulated in the resin package 12, the completed semiconductor device has a thickness about as large as 1 mm. Such a thickness is about the same as the thickness of the thin type packages widely used in recent years, which suggests how hard it could be to reduce the size of semiconductor devices having such a chip-layered body.
Meanwhile, semiconductor chips with large thickness in a semiconductor device could impede thermal radiation from the semiconductor chips, and therefore the heat radiation property of the semiconductor device as a whole could be lowered.
In view of the foregoing, it is an object of the present invention to reduce the thickness of a chip-layered body forming a semiconductor device, and allow the semiconductor device to have a reduced size and improved heat radiation property.
In order to achieve the object, the semiconductor device according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface, and a second semiconductor chip provided with a second electrode on a second main surface. The first and second semiconductor chips are integrated with one another so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip has a thickness smaller than a thickness of the first semiconductor chip.
In the semiconductor device according to the present invention, since the second semiconductor chip integrated facedown with the first semiconductor chip has a thickness smaller than that of the first semiconductor chip, a chip-layered body including the first and second semiconductor chips may have a reduced thickness. The package structure including the chip-layered body encapsulated in a resin can thus be thinner, which allows the semiconductor device to have a reduced size and improved heat radiation property.
In the semiconductor device according to the present invention, the second semiconductor chip preferably has the thickness equal to or smaller than xc2xd of the thickness of the first semiconductor chip.
In this way, the package structure for the chip-layered body can be made thinner, so that the semiconductor device can have a more reduced size and higher heat radiation property.
In the semiconductor device according to the present invention, a resin layer is preferably provided between the first and second main surfaces. Alternatively, a resin package to encapsulate the first and second semiconductor chips is preferably provided.
In this way, the chip-layered body including the first and second semiconductor chips can have improved reliability.
In the semiconductor device according to the present invention, an area of the first main surface is larger than an area of the second main surface, and a third electrode is provided outside a region of the first main surface opposed to the second main surface. A surface opposite to the first main surface of the first semiconductor chip is adhered to a die pad, a lead is provided adjacent to the die pad, and the lead and the third electrode are connected through a bonding wire. The first semiconductor chip, the second semiconductor chip and the bonding wire may be encapsulated in a resin package. In this case, a distance from the first main surface to a surface opposite to the second main surface of the second semiconductor chip is preferably smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface. In this way, a semiconductor device including a chip-layered body of the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.
A semiconductor device manufactured by a first manufacturing method according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The method includes a first step of integrating the first and second semiconductor chips by arranging the first and second main surfaces to be opposed to one another and electrically connecting the first and second electrodes, and a second step of polishing the second semiconductor chip integrated with the first semiconductor chip from the opposite side of the second main surface, so that the thickness of the second semiconductor chip is made smaller than the thickness of the first semiconductor chip.
According to the first method, after the first and second semiconductor chips are integrated to be opposed to one another, the second semiconductor chip is polished from the opposite side of the main surface (circuit forming surface), so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip. Therefore, the thickness of the chip-layered body including the first and second semiconductor chips can be reduced, so that the package structure including the chip-layered body encapsulated in a resin can have a reduced thickness, which permits the semiconductor device to have a reduced size and improved heat radiation property.
By the first method, the first step preferably includes the step of forming a resin layer between the first and second main surfaces.
In this way, the chip-layered body including the first and second semiconductor chips may have improved reliability.
By the first method, the second step preferably includes the step of reducing the thickness of the second semiconductor chip to at most xc2xd of the thickness of the first semiconductor chip.
In this way, the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and higher heat radiation property.
By the first method, an area of the first main surface is larger than an area of the second main surface, a third electrode is provided outside a region of the first main surface opposed to the second main surface. The second step may precede the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, arranging a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire. In this case, the second step preferably includes the step of allowing a distance from the first main surface to a surface of the second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface to the highest position of the bonding wire on the first main surface. In this way, the semiconductor device provided with the chip-layered body including the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.
A semiconductor device manufactured by a second manufacturing method according to the present invention includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The method includes a first step of integrating a semiconductor wafer to be a plurality of the first semiconductor chips and a plurality of discrete second semiconductor chips by arranging the first main surface of each first semiconductor chip in the semiconductor wafer to be opposed to the second main surface of each second semiconductor chip and electrically connecting the first electrode on each first semiconductor chip in the semiconductor wafer and the second electrode on each second semiconductor chip, a second step of polishing the second semiconductor chip integrated with the semiconductor wafer from an opposite side of the second main surface so that a thickness of each second semiconductor chip is smaller than a thickness of the semiconductor wafer, and a third step of separating the semiconductor wafer integrated with the second semiconductor chips into a plurality of discrete first semiconductor chips, thereby forming a plurality of chip-layered bodies each including a discrete first semiconductor chips and a discrete the second semiconductor chips integrated with one another.
By the second method, in addition to the effects brought about by the first method, the following effect results. More specifically, a plurality of chip-layered bodies, in other words a plurality of semiconductor devices having a reduced size and improved heat radiation property can readily be manufactured simply by separating a semiconductor wafer into a plurality of discrete first semiconductor chips.
By the second method, the first step preferably includes the step of forming a resin layer between the first main surface of each first semiconductor chip in the semiconductor wafer and the second main surface of each second semiconductor chip.
In this way, the chip-layered body including the first and second semiconductor chips can have improved reliability.
By the second method, the second step preferably includes the step of reducing the thickness of each second semiconductor chip to at most xc2xd of the semiconductor wafer.
In this way, the package structure including the chip-layered body can have a more reduced thickness, so that the semiconductor device can have a more reduced size and improved heat radiation property.
By the second method, an area of the first main surface is larger than an area of the second main surface. A third electrode is provided outside a region of the first main surface opposed to the second main surface. After the third step, the chip-layered bodies may each be subjected to the steps of adhering a surface of the first semiconductor chip opposite to the first main surface to a die pad, providing a lead adjacent to the die pad and electrically connecting the lead and the third electrode through a bonding wire, and forming a resin package to encapsulate the first semiconductor chip, the second semiconductor chip and the bonding wire. In this case, the second step preferably includes the step of arranging a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to a surface of each second semiconductor chip opposite to the second main surface to be smaller than a distance from the first main surface of each first semiconductor chip in the semiconductor wafer to the highest position of the bonding wire on the first main surface. In this way, the semiconductor device including the chip-layered body of the first and second semiconductor chips placed on a lead frame can surely have a reduced size and improved heat radiation property.